Homebuilt Hardware

Digital Delay Rev.0

Posted in Synth DIY by ryan on the June 23rd, 2012

This page describes my first experiment with a digital delay. It is the first revision with at least one more to come.

Several years ago, after working with the PT delay chips, I had the idea of doing another type of digital delay. The idea is to get something with higher sound quality and more control over the delay time by sampling with a normal ADC and DAC at a very high but variable rate. Those fast ADCs were expensive at the time and they still are not cheap, but recently I found a good one for about $13 each. The ADS8329 is 16bit at 1MHz sample rate and good specs. Below is a block diagram of how the design was built

Digital Delay Block Diagram

The microcontroller used is a LPC1768 ARM Cortex M3 running at 100MHz. The main loop samples a 2 channel ADC which are used for delay time (sample rate) and delay length (number of samples). These are sampled at a few KHz. The values read from these are stored and used in repetitive interrupt timer (RIT). The RIT interrupt handler samples the audio ADC, stores the sample in the off chip SRAM and puts an old sample on the DAC. I currently have this coded in C and originally had the intention to convert it to assembly until I realized I would need a hardware revision.

The C version can run the delay with a sample rate range of about 48KHz to just under 500KHz. The delay line length can be varied from just a few samples up to 512K samples. There is a switch input that sets the range that the length can be varied. In short mode the controls provide a delay range of a few microseconds to a few hundred milliseconds. In the long range the controls provide a delay range of a few hundred milliseconds to about 12 seconds.

The results of this test have been great. It works well as a flanger or echo. Its a lot of fun to play with and I can’t wait to see what I can do with multiple delays. I realized the microcontroller was not going to be quick enough to run at the full 1MHz so i already planned for a new version. Part of the problem is that there is no external SRAM interface on the LPC1768. NXP now has a new Cortex M3 that has that. A few other issues need to be addressed in the analog section. I made a mistake on the ADC driver and that part of the layout that results in some noise.

The next revision will probably use an FPGA instead of the microcontroller. I need a way to smoothly change from one delay line length to another and I don’t think I can get enough instructions processed to do that and still run at the full 1MHz. Besides, i have been waiting for a good excuse to do an FPGA design for some time. Expect it to be a while, its rather expensive to build these prototypes with 4-layer boards. I will publish the design once its built and tested.